This invention relates to computer system design and particularly to data transfers through a shared chip to chip interface.
Heretofore, allocating usage for a shared interface that sends data between two chips at two different speeds depending on the type of transfer resulted in all transfers taking place at a slower rate of speed. This solution is for scenarios where an interface is shared by several different requesters, some which transfer data at one data shot every clock cycle (full or high speed), and some which transfer data at one data shot every other cycle (half or low speed). Requests that are designed to transfer data at full speed are more critical to system performance than requests that are designed to transfer data at half speed.
A simple solution is to block a high speed transfer request when an ongoing low speed transfer is going on. However, this would result in a solution that has performance critical requests stuck behind less critical half speed transfers that last twice as long and only use half the available bus bandwidth. This is a severe performance degradation.